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Developing AMBA AXI-Compliant Modules for System-on-Chip Designs


The AMBA AXI group of protocols is widely used in many ASIC and FPGA designs. The very high level of complexity in modern and future designs demands new and innovative techniques that simplify the design process, thus speeding up time-to-market and ease maintenance of the design, without sacrificing quality.

Just having knowledge of these protocols is insufficient to produce an efficient, optimised, and cost-effective design. We introduce all the basics required in bus communications protocol design, enabling participants to have the fundamentals required to embark on any protocol design project. Furthermore, we delve into the inner workings of the AMBA AXI4-Lite and AXI4-Stream protocols, while presenting the concepts using simple yet state-of-the-art TLM/BFM techniques, resulting in high-quality, efficient, and cost-effective designs.

Participants will also learn how to interface between several AXI4-compliant subsystems, using simple TLM/BFM techniques. We finally demonstrate how modules could easily communicate with one another via the AXI4 bus.

Course highlights

Participants will have practical design experience using industry-standard logic simulators (Mentor Graphics QuestaSim or Synopsys VCS-MX), logic synthesis tools (Synopsys Design Compiler or Xilinx Vivado), and development boards with Xilinx Zynq or Altera Cyclone V FPGAs.

What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
  • Read and understand bus protocol specifications.
  • Develop models based on bus specifications.
  • Understand, develop, and simulate protocols from the AMBA AXI4 group of protocols.
  • Synthesise, implement, and verify the design against the specification.

Who Should Attend

This course is particularly suited for engineers involved in ARM-based system-on-chip designs, verification and testing.


Participants should have a diploma/degree in electronics (or related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesisable digital systems or simulation testbenches. Participants are strongly encouraged to attend the following course(s) prior to attending this course:

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course Duration

Three (3) days, 0900 to 1700.

Course Structure

  1. Introduction
    • Introduction to System-on-Chip architectures, bus architectures, and communications protocols.
    • Introduction to the AMBA AXI4 group of protocols.
  2. Bus Architecture Designs
    • Concept of interface ports and interconnect routings.
    • Revision of TLM and BFM techniques.
    • Timing diagrams.
  3. The AMBA AXI4 Specification
    • AXI architecture: component topology, transactions, and memory management.
    • The AXI4 protocols: AXI4, AXI4-Lite, and AXI4-Stream protocols.
    • Signal descriptions for AXI4, AXI4-Lite, and AXI4-Stream.
  4. Bus Modelling and Functional Simulations
    • Revision on bus functional modelling (BFM).
    • Hands-on Practical 1: Describing AXI4-Lite protocol as a BFM.
    • Setting up Mentor Graphics QuestaSim, or Synopsys VCS-MX for simulations.
    • Hands-on Practical 2: Simulating the AXI4-Lite protocol BFM.
    • Hands-on Practical 3: Simulating the AXI4-Stream protocol BFM.
  5. BFM synthesis
    • Setting up the Synopsys Design Compiler / Xilinx Vivado / Quartus synthesis and auto-placement-and-routing (APR) tools.
    • Hands-on Practical 4: Synthesising the AXI4-Lite protocol BFM.
    • Hands-on Practical 5: Synthesising the AXI4-Stream protocol BFM.
  6. Full-chip Integration of SoC Components
    • Overview of the SoC system-level architecture.
    • Hands-on Practical 6: Integrating AXI4-Lite / AXI4-Stream TLM/BFM with the ARM Cortex-A9 processor.
  7. Hardware System-level Verification
    • Overview of hardware verification flow for post-PAR.
    • Setting up Xilinx ChipScope Pro / Quartus SignalTap II.
    • Hands-on Practical 7: Full-chip hardware verification of AXI4-Lite / AXI4-Stream protocol design.
  8. Hardware-software Co-verification
    • Setting up the programming environment.
    • Developing C programs for functional testing.
    • Hands-on Practical 8: Functional verification of AXI4-Stream TLM/BFM.
  9. [optional] Synthesis and Layout Optimisation Techniques
    • Optimising for area and power: RTL optimisation techniques.
    • Optimising for speed: static timing analysis (STA), floorplanning and manual placement techniques for high-performance design.
    • Specifying timing and area constraints.
    • Hands-on Practical 9: Optimising the design for area, power, and speed.

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