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Digital Systems Design and Simulations with VHDL

Synopsis

Digital RTL design plays an important role in our everyday lives. From simple products such as a USB mouse, to more complex ones such as mobile cellphones and computers, we use these products everyday. All of these products require digital logic designers to create.

VHDL is a popular hardware description language (HDL), mostly used to describe and verify digital electronic circuits. Because of the deterministic nature of VHDL, almost every mission-critical and safety-critical industrial electronics as well as all main digital electronics used in military, automotive, avionics, and aerospace require the use of VHDL as the primary hardware design language. We introduce the fundamental concepts of VHDL, and apply these concepts for digital logic simulation and synthesis.

Participants will get to have an understanding of digital logic design in VHDL, and use industry tools to simulate and synthesise their designs.

Course highlights

Participants will have practical design experience using industry-standard logic simulators (e.g. Synopsys VCS-MX), logic synthesis and automated placement-and-routing tools (e.g. Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus), and development boards from either Xilinx or Altera.

What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Who Should Attend

This course is particularly suited for engineers involved in HDL-flow digital design simulation, verification and testing.

Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems.

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course Duration

Three days, 0900 to 1700.

Course Structure

  1. Overview
    • Overview of FPGA architecture.
    • FPGA / Digital ASIC common design flow.
    • Overview of FPGA design, simulation, and hardware verification tools.
  2. Introduction to VHDL
    • What is VHDL?
    • Why use VHDL?
    • VHDL Basics: basic structure / shape of VHDL.
    • Hands-on Lab 1: Design a simple block with the correct VHDL structure.
  3. Logic systems
    • Binary logic.
    • Multi-valued logic.
    • The ieee.std_logic_1164 nine-value logic system.
  4. Data structures for synthesis
    • VHDL's strong typing feature.
    • Scalar types vs. composite types.
    • Structures from ieee.std_logic_1164.
    • Structures from ieee.standard.
    • Extended vectors/composite structures from VHDL-2008.
    • Custom data structures: type, subtype.
    • Vectors/arrays.
    • Hands-on Lab 2 & 3: Construct memory structures using VHDL arrays.
    • Record types.
  5. Type conversions
    • Converting between (un)signed <=> integer.
    • Converting between std_logic_vector <=> (un)signed.
    • Converting between std_logic_vector <=> integer.
  6. Subprograms
    • Functions.
    • Procedures.
    • Subprogram overloading.
  7. Operators
    • Assignment operators (<=, :=)
    • Common comparison operators (=, /=, <, >, <=, >=).
    • Operator overloading.
  8. Hardware modelling
    • Overview of behavioural vs. structural modelling.
    • Structural design for synthesis
      • Component instantiations.
      • Hands-on Lab 4: Component instantiations.
      • Direct-entity instantiations.
      • Hands-on Lab 5: Direct-entity instantiations.
      • Automatic duplication of iterative structures using for-generate statements.
      • Hands-on Lab 6: Generate statements to iteratively duplicate structures.
      • Hands-on Lab 7: Embedding an Altera GX / Xilinx GTX transceiver IP core using VHDL.
    • Behavioural design for synthesis
      • Overview of concurrent vs. sequential techniques.
      • Lab Exercise 8: Distinguish between concurrent and sequential structures.
      • Processes for synthesis
        • Process sensitivity lists.
        • Sequential/cascaded design techniques using conditional statements: if-[elsif]-[else] statement, case statement, when-[else] clause, with-select-when statement.
        • Matching conditional operators and statements.
      • Finite-state machine (FSM) design.
      • Hands-on Lab 9 & 10: Design the basic building blocks of a communications protocol statemachine.
  9. Functional verification
    • Hands-on Lab 11: Design of generic testbench for software simulation and hardware BiST.
    • Hands-on Lab 12: Functional simulation with Synopsys VCS-MX or Mentor Graphics ModelSim.
    • Hands-on Lab 13: Hardware verification using BiST; correlation between measurements and simulation.
  10. Overview of advanced topics
    • VHDL package design: create your own library.
    • Protected types and shared variables.
    • VHDL generics for highly-parameterisable designs. This will also cover type generics and subprogram generics.
    • VHDL configurations for reconfigurable designs/testbenches with multiple architectures.
    • Synthesis attributes (vendor-specific and predefined).
    • Synthesis pragmas/directives for conditional compilation.
    • IP source encryption.
    • VHDL's determinism built into the language (discussion).
    • Simulation-only techniques for testbench design:
      • Access types.
      • File I/O.
      • Custom resolution functions.
      • External/hierarchical names.
      • Force and release assignments.
      • Assertion-based verification (ABV): Temporal assertions with embedded PSL.
      • Open-source VHDL Verification Methodology (OS-VVM) framework for constrained random verification (CRV) and intelligent coverage.

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