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Transaction-level Modelling (TLM) and Bus Functional Modelling (BFM) with VHDL

Synopsis

As systems-on-chips (SoC) integrate increasingly more features on a chip, the sheer complexity demands a shift in design paradigm. With multiple inter-module routing groups within an SoC, it is no longer feasible for bus interfaces to be designed using conventional low-level signalling methodologies.

We introduce the concept of transaction-level modelling (TLM) and bus functional modelling (BFM) in this course, which are methods to encapsulate low-level signalling into high-level transactions. TLMs/BFMs simplify your testbenches and system-level designs by separating the low-level bus models (BFMs) from the higher-level transactor abstractions (TLMs), making your testbenches/SoC designs easier to manage and maintain. These concepts are very useful for both simulation testbenches as well as synthesisable SoC bus interface designs.

Participants will have an in-depth understanding of TLMs and BFMs, and will design transactors and bus functional models for a simple FIFO application, commonly found in numerous real-world applications. We demonstrate how modules could easily communicate with one another via a bus interface designed using TLM and BFM techniques. Communicating between two individual testbench/SoC components is as simple as making a procedure-call statement.

Course highlights

Participants will have practical design experience using industry-standard logic simulators (e.g. Mentor Graphics QuestaSim, or Synopsys VCS-MX), logic synthesis tools (e.g. Synopsys Design Compiler, or Xilinx Vivado), and development boards with Xilinx Zynq or Altera Cyclone V FPGAs.

What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Who Should Attend

This course is particularly suited for engineers involved in ARM-based system-on-chip designs, verification and testing.

Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesisable digital systems or simulation testbenches. Participants are strongly encouraged to attend the following course(s) prior to attending this course:

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course Duration

Three (3) days, 0900 to 1700.

Course Structure

  1. Introduction
    • Overview of testbenches and systems-on-chip (SoC) architectures.
    • Overview of bus architecture designs.
    • Overview of transaction-level modelling (TLM).
    • Overview of bus functional modelling (BFM).
    • Overview of available VHDL TLM/BFM frameworks.
  2. Transactor design
    • Concept of transactions.
    • Concept of TLM and its applications.
    • Review of VHDL procedures.
    • Typical example of a transaction-level model (transactor).
    • Generic design for transactors.
    • Hands-on Practical 1: Designing a FIFO master transactor.
  3. Bus functional model design
    • Concept of bus functional models (BFM).
    • Revision on finite-state machines (FSM).
    • Typical example of a BFM.
    • Encapsulating low-level protocol signalling using a BFM.
    • Hands-on Practical 2: BFM design of the FIFO Master using non-synthesisable VHDL.
    • Hands-on Practical 3: BFM design of the FIFO Master using synthesisable VHDL.
  4. Transactor and BFM simulation
    • Simulation requirements and setup.
    • Hands-on Practical 4: Simulating the FIFO Master TLM/BFM models.
  5. Transactor and BFM synthesis and implementation
    • Configuring tools for synthesis.
    • Hands-on Practical 5: Synthesising the FIFO Master TLM and BFM.
    • Automatic-placement and routing (APR), design partitioning, and design assembly.
    • Configuring tools for APR and design assembly.
    • Hands-on Practical 6: Implementing the FIFO Master TLM/BFM design.
  6. Transactor and BFM hardware verification
    • Hardware verification flow for post-silicon verification.
    • Overview of the development board, clock and reset assignments, JTAG set-up.
    • Configuring tools for verification.
    • Hands-on Practical 7: Verifying the FIFO TLM/BFM design on hardware.
  7. Optimisation for Area and Power
    • RTL optimisation techniques.
    • Specifying area constraints, floorplanning, and design partitioning.
    • Configuring and using area and power optimisation tools.
    • Hands-on Practical 8: Optimising the design for area and power.
  8. Speed Optimisation Techniques
    • Manual placement techniques for high-performance design.
    • Concept of timing closure.
    • Specifying timing constraints.
    • Static timing analysis (STA).
    • Configuring and using speed optimisation tools.
    • Hands-on Practical 9: Optimising for speed.

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