VHDL for Synthesis

Synopsis

Field Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture.

This course introduces the complete FPGA development flow and environment with VHDL. The emphasis here is on the subset of VHDL that is synthesizable -- i.e. capable of producing hardware -- rather than the entire HDL. Proper, generic hardware description style and implementation techniques are introduced throughout the course.

Course highlight
Participants will have practical design experience using an FPGA development board (Xilinx/Altera), together with the use of FPGA simulation and synthesis tools.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Familiarise with FPGA development tools for design entry, analysis and simulation (Xilinx Vivado, Altera Quartus, Mentor Graphics ModelSim, Synopsys VCS-MX)
Know the fundamentals of VHDL, with particular emphasis on synthesizable constructs (i.e. able to generate hardware)
Describe combinational and sequential circuits in a structural and behavioural manner
Develop digital systems in a hierarchical and modular nature to aid testing, debugging and hardware reuse
Learn and use VHDL constructs for simulation and verification with testbenches
Describe the operation of sequential circuits in the Register Transfer Level (RTL) notation
Describe control flow with Finite-State Machines (FSM) and implement them in VHDL

Who should attend

This course is particularly suited for engineers involved in digital design and testing who are new to the HDL flow.

Prerequisite

Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. This course is the recommended prerequisite for the following advanced VHDL synthesis courses:

Register Transfers and Sequencing in VHDL
Transaction-level Modelling and Bus Functional Modelling
Developing AMBA AXI-compliant Modules for System-On-Chip Designs

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with hands-on practical for maximum understanding.

Course duration

Four days, 0900 to 1700.

Course structure

Introduction
- IC/FPGA design flow
- HDL design flow (front-end design)
- History of VHDL
- Key concepts, philosophy, and doctrine
- Determinism
Basic VHDL 1
- Basic language constructs
- std_logic_1164 nine-value logic system
- Operators
- Data types and representation
- VHDL’s strong typing
- Type safety: Benefits of strong typing
- Type conversions
- Hands-on Practical: My first VHDL design with Quartus II
Basic VHDL 2: VHDL Data Structures for Synthesis
- Concept of scalar types vs. composite types
- Custom data types: type, subtype
- Synthesisable predefined data types and structures
- New synthesisable data types from VHDL-2008
- More on composite types: enumerated types, aggregates and array slices, record types
- Concatenation
- Repetition: functional and structural repetitions
- RAMs and ROMs
- Hands-on Practical: Design memory structures using VHDL arrays
Overview of Hardware Modelling Techniques
- Behavioural vs. structural modelling
- Behavioural modelling techniques: concurrent vs. sequential design
Structural Design for Synthesis
- Structural HDL modelling
- Component instantiation
- Hands-on Practical: Instantiate a given component in your design
- Direct-entity instantiation
- Hands-on Practical: Directly instantiate a given submodule
- Hands-on Practical: Directly embed an Xilinx GTX / Altera GX transceiver IP core using VHDL
- Hierarchical design and Modularisation
- Basic generics (Parameterisation)
- Automatic generation of repeating structures
- Hands-on Practical: Iteratively duplicate a given submodule a specified number of times
Behavioural Design for Synthesis: Sequential Techniques
- Register basics
- Processes for synthesis
- Sequential statements
- Conditional signal assignments using sequential techniques
- Verilog’s blocking and non-blocking statements: a VHDL explanation
- Process sensitivity lists
- New matching conditional operators from VHDL-2008
- Inference of the basic building blocks: registers, latches, multiplexers, and comparators
- Hands-on Practical: Combinatorial logic using sequential techniques
- Counters
- Hands-on Practical: Design an up/down counter using sequential techniques
- Shift registers
Behavioural Design for Synthesis: Concurrent Techniques
- Concurrent statements
- Conditional signal assignments using concurrent techniques
- Hands-on Practical: Combinatorial logic using concurrent techniques
- Hands-on Practical: Design an up/down counter using concurrent techniques

State Machines
- Register transfer operations
- Finite-state Machines (FSM)
- Hands-on Practical: Design a serial transceiver (transmitter)
- Hands-on Practical: Design a serial receiver
Basics of Functional Verification
- Basic testbench methods
- Hands-on Practical: Simulate with Synopsys VCS-MX
- Hands-on Practical: Verify design on hardware with SignalTap
Overview of Advanced Topics
- VHDL package design: create your own library
- Subprograms: Functions & Procedures
- Access types
- Protected types and shared variables
- Advanced generics: Type generics, Subprogram generics, Package generics
- Configurations
- Synthesis attributes (vendor-specific and predefined)
- Synthesis pragmas/directives
- IP source encryption
- Custom resolution functions
- Simulation-only techniques for testbench design: Files I/O, External/hierarchical names, Force and release assignments, Assertion-based verification (ABV), Constrained random verification (CRV), Functional coverage (FC)