(+65)-8832-4546 | (+65)-8832-4546 | Contact Us

VHDL Simulations and Testbenches


The ubiquity and complexity of commercial, professional and industrial digital systems has been increasing exponentially over the years as we integrate more and more features into these systems. Coupled with the ever shortening time-to-market and the proliferation of systems in safety critical areas, the immense challenges of engineers are to ensure their complex designs are error free and conform to the desired functionality. These challenges has made verification, especially at the pre-silicon stage, a vital stage in the design process.

The need for a systematic approach towards verifying digital systems has given rise to advanced testbench verification methodologies such as OS-VVM, OVM, UVM and AVM. This course introduces the key testbench concepts and verification framework of OS-VVM, that allow engineers to systematically and accurately validate designs with minimal test cases. The course covers the simulation of digital systems and the design of proper testbenches for verification. Ultimately, this course aims to arm engineers with a powerful tool to ensure their designs can be properly tested in a timely manner.

Course highlights

Participants will have practical design experience using industry-standard logic simulators (e.g. Synopsys VCS-MX or Mentor Graphics QuestaSim/ModelSim).

What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Who Should Attend

This course is particularly suited for engineers involved in HDL-flow digital design simulation, verification and testing.


Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. Knowledge in VHDL/Verilog for developing synthesizable digital systems or simulation testbenches is helpful but not required.

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course Duration

Three days, 0900 to 1700.

Course Structure

  1. Introduction
    • IC/FPGA design and verification flow.
    • The Design Under Verification (DUV).
    • Overview of testbench components.
  2. Stimuli vector generator design
    • Concept of test vector generation, types of stimuli (directed, pseudorandom).
    • Unconstrained vs. constrained randomisation.
    • Unconstrained randomisation of stimuli.
    • Hands-on Practical 1: Unconstrained random stimuli vector generator design and simulation.
    • Constrained random verification (CRV).
    • Hands-on Practical 2: Constrained random stimuli vector generator design and simulation.
    • File I/O (input only).
    • Hands-on Practical 3: Reading stimuli from a file.
  3. Transaction monitor design
    • Concept of transaction monitoring.
    • Simple (non-temporal) assertions-based verification (ABV).
    • Hands-on Practical 4: Transaction monitor design using non-temporal assertions.
  4. Response checker design
    • Concept of response checking.
    • Scoreboards.
    • Hands-on Practical 5: Response checker design using scoreboards logged to simulator’s console.
    • File I/O (output only).
    • Hands-on Practical 6: Response checker design using scoreboards logged to a file.
  5. Overview of advanced testbench techniques
    • Temporal assertions-based verification (ABV) with Property Specification Language (PSL).
    • Functional coverage: an introduction to OS-VVM's intelligent coverage-driven constrained randomisation.
    • Transaction-level modelling (TLM) and bus functional modelling (BFM).

Email us to ask for a quotation.