VHDL Subprograms for Synthesis and Simulations

Synopsis

VHDL is a popular hardware description language, mostly used to describe and verify electronic circuits. We introduce the concept of subprograms, which is useful for both simulation and synthesis. Participants will get to have an understanding of what functions and procedures are, and be able to apply these concepts in real designs that involve digital simulation or synthesis.

Course highlights

Participants will have practical design experience using industry-standard logic simulators (e.g. Synopsys VCS-MX or Mentor Graphics QuestaSim/ModelSim), logic synthesis tools (e.g. Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus), and development boards from either Altera or Xilinx.

What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Learn how to use subprograms for synthesis and simulation.
Use VHDL subprograms in digital designs.
Simulate and synthesise designs that use VHDL subprograms.

Who Should Attend

This course is particularly suited for engineers involved in HDL-flow digital design simulation, verification and testing.

Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesizable digital systems or simulation testbenches.

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course Duration

Two days, 0900 to 1700.

Course Structure

Introduction
- Overview of subprograms.
- When to use functions and procedures?
VHDL Functions
- Basic syntax of a function.
- Hands-on Practical 1: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
- Hands-on Practical 2: Synthesis with Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus.
VHDL Procedures
- Basic syntax of a procedure.
- Hands-on Practical 3: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
- Hands-on Practical 4: Synthesis with Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus.
[optional]: Advanced Topics
- Subprogram overloading.
- Hands-on Practical 5: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
- Hands-on Practical 6: Synthesis with Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus.
- Subprogram generics.
- Hands-on Practical 7: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
- Impure functions.
- Hands-on Practical 8: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.