Daniel Kho is a VHDL and FPGA expert with over 24 years in FPGA design and ASIC design, solving complex hardware problems for engineering teams across DSP, video and AI workloads. As Founder and CTO of LogikHaus, he leads the company's FPGA design services and the development of its Video and AI Imaging Solutions, including the core video processor IP (VPU), AI core integration, and communications IP such as FFT, QPSK/QAM and MIPI C-PHY.
His verification work is built on OSVVM and UVM, spanning VHDL scoreboards, transaction-level modelling and constrained-random verification. He has also designed and verified cryptographic hardware, including a Blowfish core, and pseudorandom number generators based on Galois-field LFSRs and the Mersenne Twister algorithm.
Daniel is the inventor on a Malaysian patent application (PI2022002780) for a method and system of parallel image kernel processing, the technique behind the high-speed video processing in LogikHaus's VPU. He is also a Certified Professional Trainer (IPMA UK) and Certified Train-the-Trainer (HRDF Malaysia), and teaches the VHDL and FPGA design courses at LogikHaus Academy.
Project Highlights
Parallel Image Kernel Processing for a High-Speed VPU
The video processor IP at the core of LogikHaus's imaging solutions has to apply image kernel operations (the convolution-style filtering used in real-time video and AI pre-processing) across high-resolution streams without stalling the pipeline. Daniel architected a method for running these kernel operations in parallel within the FPGA fabric, avoiding the sequential bottleneck that conventional single-pass implementations hit at high frame rates. The approach is now the subject of a filed patent application and underpins the VPU's real-time high-resolution processing.
OSVVM/UVM Verification Framework for Communications IP
Communications IP blocks such as FFT, QPSK/QAM modulation and MIPI C-PHY interfaces need verification environments that exercise a very large space of protocol and signal edge cases before tape-out. Daniel built VHDL scoreboards and transaction-level models under OSVVM and UVM to drive constrained-random verification across these blocks, catching corner-case protocol violations that directed testing alone would be unlikely to surface.
Areas of Expertise
Frequently Asked Questions
Who is Daniel Kho?
Daniel Kho is the Founder and CTO of LogikHaus, a VHDL and FPGA specialist with over 24 years in FPGA design, ASIC design and DSP. He leads development of the company's video processor IP, AI core integration and communications IP.
What FPGA design work has Daniel Kho done?
He architected FPGA-based video processor IP for real-time high-resolution video, filed a Malaysian patent application for parallel image kernel processing, built OSVVM and UVM verification frameworks for communications IP, and designed cryptographic hardware including a Blowfish core.
Does Daniel Kho teach VHDL and FPGA courses?
Yes. Daniel is a Certified Professional Trainer (IPMA UK) and Certified Train-the-Trainer (HRDF Malaysia). He teaches the VHDL and FPGA design courses at LogikHaus Academy and has delivered VHDL, SystemVerilog and digital design training across Southeast Asia.
How can I work with Daniel Kho on an FPGA project?
Daniel leads FPGA and ASIC design engagements at LogikHaus. Contact us with a short description of your project and requirements to discuss scope.