Daniel Kho is a VHDL expert and FPGA expert with over 24 years in FPGA design and ASIC design, solving complex hardware challenges for engineering teams across DSP, video, and AI workloads. As Founder and CTO of LogikHaus, he leads development of the company's Video and AI Imaging Solutions — including the core video processor IP (VPU), AI core integration, and communications IP such as FFT, QPSK/QAM, and MIPI C-PHY implementations.
His verification work is built on OSVVM and UVM methodologies, spanning VHDL scoreboards, transaction-level modelling, and constrained random verification. He has also designed and verified cryptographic hardware, including a Blowfish cryptographic core, and pseudorandom number generators based on Galois-field LFSRs and the Mersenne twister algorithm.
Daniel has a patent application filed in Malaysia (PI2022002780) for a method and system of performing parallel image kernel processing — core to the high-speed video processing work at the heart of LogikHaus's VPU technology. As LogikHaus's resident FPGA expert, he is also a Certified Professional Trainer (IPMA UK) and Certified Train-the-Trainer (HRDF Malaysia), delivering VHDL, SystemVerilog, and digital design training across Southeast Asia.
Project Highlights
Parallel Image Kernel Processing for High-Speed VPU
The video processor IP (VPU) at the core of LogikHaus's imaging solutions needed to apply image kernel operations — convolution-style filtering used in real-time video and AI pre-processing — across high-resolution streams without stalling the pipeline. As LogikHaus's FPGA expert, Daniel architected a method for performing these kernel operations in parallel within the FPGA fabric, avoiding the sequential bottleneck that conventional single-pass kernel implementations run into at high frame rates. The approach is now the subject of a filed patent application and underpins the VPU's ability to process high-resolution video in real time.
OSVVM/UVM Verification Framework for Communications IP
Communications IP blocks — including FFT, QPSK/QAM modulation, and MIPI C-PHY interfaces — require verification environments that can exercise a very large space of protocol and signal-integrity edge cases before tape-out. Drawing on his depth as an FPGA expert, Daniel built VHDL scoreboards and transaction-level models under OSVVM and UVM methodologies to drive constrained-random verification across these blocks, catching corner-case protocol violations that directed testing alone would be unlikely to surface.
Areas of Expertise
Frequently Asked Questions
- Who is Daniel Kho?
- Daniel Kho is the Founder and CTO of LogikHaus, a VHDL and FPGA specialist with over 24 years in FPGA design, ASIC design, and DSP, leading development of the company's video processor IP, AI core integration, and communications IP.
- What FPGA design work has Daniel Kho done?
- Daniel has architected FPGA-based video processor IP for real-time high-resolution video, filed a Malaysian patent application for parallel image kernel processing, built OSVVM/UVM verification frameworks for communications IP, and designed cryptographic hardware including a Blowfish core.
- What makes Daniel Kho an FPGA expert?
- Daniel Kho is an FPGA expert with over 24 years of hands-on FPGA and ASIC design experience, a filed patent application for parallel image kernel processing, and verification frameworks built on OSVVM and UVM. He is also a Certified Professional Trainer who has taught FPGA and VHDL design across Southeast Asia.
- Why choose LogikHaus's FPGA expert?
- As LogikHaus's FPGA expert and Founder/CTO, Daniel Kho brings 24+ years of FPGA and ASIC design experience directly to every engagement, from architecting the company's video processor IP to leading its OSVVM/UVM verification methodology, backed by a filed Malaysian patent for parallel image kernel processing.