Who is the FPGA expert at LogikHaus?

Daniel Kho, Founder & CTO of LogikHaus, is the company's lead FPGA and VHDL expert, with 24+ years designing FPGA, ASIC and DSP systems including video processor IP cores and communications IP.

What does a VHDL expert do?

A VHDL expert designs, models and verifies digital hardware described in VHDL, from RTL logic and bus interfaces to full FPGA and ASIC implementations, and builds verification environments using methodologies such as OSVVM and UVM.

What is a parasitic extraction expert?

A parasitic extraction (PEX) expert analyses the resistance, capacitance and coupling effects introduced by chip layout and interconnect, using dedicated extraction tools, to ensure a design's real-world electrical behaviour matches its intended timing and signal integrity.

What does an ASIC LVS expert check?

An ASIC LVS (Layout Versus Schematic) expert verifies that a chip's physical layout exactly matches its intended circuit schematic, catching shorts, opens and connectivity errors before tape-out.

What is an ASIC EDA flow expert?

An ASIC EDA flow expert builds and qualifies the electronic design automation toolchains, spanning extraction, LVS, static timing analysis and PDK qualification, that semiconductor teams rely on to move a design from RTL to silicon.

Does LogikHaus offer FPGA and ASIC design training?

Yes. LogikHaus provides classroom and dedicated training in VHDL, SystemVerilog, UVM, OSVVM, digital signal processing and digital communications, delivered by our in-house VHDL and FPGA experts.

About Us - VHDL, FPGA, RFIC & Parasitic Extraction Experts

LogikHaus is a fabless ASIC and FPGA technology company, founded in Malaysia in February 2019, which moved its head office to Singapore in 2024. We focus on AI, machine vision, motion control and robotics, video and image processing, and DSP on FPGA and ASIC. We are a small team of engineers and scientists: our VHDL and FPGA expert Daniel Kho, our parasitic extraction and ASIC LVS specialist Jeannie Lau, and our RFIC and analog IC design specialist Dr. Arjuna Marzuki. Our history goes back to Tauhop Solutions, a sole proprietorship founded in 2012 for ASIC and FPGA product design and consulting, and our core expertise remains FPGA and ASIC design for low-power, high-performance DSP, video processing and AI products.

Our team covers the complete IC design flow, from RTL design in VHDL and Verilog through physical implementation (floorplanning, routing) and sign-off verification (STA, LVS, PEX, DRC). We bring advanced verification expertise in UVM and OSVVM for both FPGA design and ASIC design, alongside mixed-signal and analog integration at the full-chip and PCB level. Our EDA automation work covers custom flow development in Perl, Python and Tcl, and our DSP and high-performance computing expertise powers hardware implementations of video, image and digital control algorithms on both FPGAs and ASICs.

We put our time and resources into the hardest problems, and that shows in our products and services. In video, the hardest challenge is sending clear video in real time, so our video processor was designed specifically to process high-resolution video quickly. See our designs and IP cores for more detail.

Our products and services span digital communications, digital control, optical communications, wireless communications, artificial intelligence and vision systems built on FPGA and GPU platforms.

Our training focuses on VHDL front-end design and verification, and we have delivered design services for cryptography, communications systems, servo control systems and memory controllers. We continue to train and hire VHDL engineers. Read our free FPGA design guide and VHDL design guide, or explore our FPGA and VHDL courses.

Our Team - Industry Experts

Daniel Kho - Founder & CTO

SMIEEE · MIES · M.Eng.Sc. (Multimedia University)

A VHDL expert and FPGA expert with over 24 years solving complex FPGA, ASIC and DSP challenges for engineering teams building real-world hardware. Daniel has led development of video processor IP cores, AI core integration, communications IP (FFT, QPSK/QAM, MIPI C-PHY) and cryptographic hardware, alongside verification frameworks built on OSVVM and UVM. He is a Certified Professional Trainer delivering VHDL, SystemVerilog and digital design training across Southeast Asia.

View FPGA expert profile LinkedIn

Jeannie Lau - Principal Analogue Microelectronics Engineer

22+ years in ASIC design enablement · GLOBALFOUNDRIES · Intel

A parasitic extraction expert and ASIC LVS expert (layout-versus-schematic verification), Jeannie specialises in circuit analysis, RC extraction and static timing analysis (STA) across StarRC, xRC and Quantus/QRC flows. As an ASIC EDA flow expert, she has developed and qualified custom extraction and LVS flows against foundry PDKs down to 14nm and 10nm process nodes, and holds an Altera Innovator Award for resolving capacitive shielding issues. At LogikHaus she leads analog design and verification at the PCB level, alongside hardware debug and embedded system verification.

View parasitic extraction expert profile LinkedIn

Dr. Arjuna Marzuki - Principal RFIC Engineer

28+ years · FIET · Chartered Engineer · Published Author

An RFIC expert and analog IC design expert with over 28 years in integrated circuit commercialisation across Hewlett-Packard, AMD, Agilent Technologies and academia. Dr. Arjuna is the author of two published books on RFIC and CMOS analog/mixed-signal circuit design, holds three patents, and is currently Associate Professor and Postgraduate Programmes Lead in Electronic Engineering at Wawasan Open University. He is a Fellow of the Institution of Engineering and Technology (FIET) and a Chartered Engineer registered with the UK Engineering Council.

View RFIC expert profile LinkedIn

Our Offices

Singapore Office

21 Woodlands Close
#06-16
Singapore 737854

Malaysia Office

35 Lebuh Lembah Permai 1
Tanjong Bungah 11200
Penang, Malaysia

India Distributor

SPEC2SILICON PVT LTD
Bettur Road, Bettur
Davanagere - 577002

Our Partners

Gowin Semiconductor

Caelus Technologies

Artengi Ltd

Frequently Asked Questions

Who is the FPGA expert at LogikHaus?: Daniel Kho, Founder & CTO of LogikHaus, is the company's lead FPGA and VHDL expert, with 24+ years designing FPGA, ASIC and DSP systems including video processor IP cores and communications IP.
What does a VHDL expert do?: A VHDL expert designs, models and verifies digital hardware described in VHDL, from RTL logic and bus interfaces to full FPGA and ASIC implementations, and builds verification environments using methodologies such as OSVVM and UVM.
What is a parasitic extraction expert?: A parasitic extraction (PEX) expert analyses the resistance, capacitance and coupling effects introduced by chip layout and interconnect, using dedicated extraction tools, to ensure a design's real-world electrical behaviour matches its intended timing and signal integrity.
What does an ASIC LVS expert check?: An ASIC LVS (Layout Versus Schematic) expert verifies that a chip's physical layout exactly matches its intended circuit schematic, catching shorts, opens and connectivity errors before tape-out.
What is an ASIC EDA flow expert?: An ASIC EDA flow expert builds and qualifies the electronic design automation (EDA) toolchains, spanning extraction, LVS, static timing analysis and PDK qualification, that semiconductor teams rely on to move a design from RTL to silicon.
Does LogikHaus offer FPGA and ASIC design training?: Yes. LogikHaus provides classroom and dedicated training in VHDL, SystemVerilog, UVM, OSVVM, digital signal processing and digital communications, delivered by our in-house VHDL and FPGA experts.

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