Explore our custom phased-locked loop (PLL) solutions

- RFIC and MMIC microchip-level low-jitter clocking solutions for PLL components, including VCO, LC Tank, charge pump, phase-frequency detectors, and digital clock control solutions

- License our RF IPs or explore our RFIC production options

- Enquire about stable production schedules - Build your ASIC PLL with us!

- PCB-level clocking solutions using existing COTS components (boards depending on US / European chips may be affected by supply disruptions)

Interface:

- IP Core version: Supports AXI4-Lite configuration

- Packaged ASIC version: Supports SPI configuration

The digital clock control logic in this line is developed in-house through our FPGA design process, with RTL written and verified by LogikHaus's VHDL experts.