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Data Protection Policy

At LogikHaus, we take your privacy seriously. We are fully committed to protecting your personal information in compliance with Singapore's Personal Data Protection Act (PDPA) 2012.

How we handle your data:

For more information on your rights under Singapore Law, please visit:

→ Singapore Statutes Online (PDPA 2012) → DLA Piper Global Data Protection Guide (Singapore)

Frequently Asked Questions

Is the VPU IP Core available in VHDL?
Yes — we license the VPU IP Core as a VHDL netlist (Vivado) or as VHDL source code, RFQ on request.
Who designed the VPU IP Core?
The VPU IP Core was architected and verified by LogikHaus's in-house FPGA expert and VHDL expert team, using an OSVVM/UVM-based VHDL design and verification methodology.
Video and AI Imaging Solutions LogikHaus FPGA & Video Processing Module
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Video and AI Imaging Solutions

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Product Overview

Ask us about our custom imaging solutions, designed in-house by our FPGA design and VHDL design team:

- Explore our real-time AI video processing solutions, built on FPGA design work led by our in-house FPGA expert

- License our digital imaging ASIC and FPGA IPs, provided in VHDL netlist or RTL, hand-written by our VHDL experts

- License our analogue imaging ASIC IPs

- Enquire about stable production schedules - Build your imaging ASIC with us!

- Explore our PCB solutions built using COTS components (boards depending on US / European chips may be affected by supply disruptions)

Interfaces:

- IP Core version: Supports AXI4-Stream data interface and AXI4-Lite configuration interface

- Packaged ASIC version: Supports native data interfaces (HDMI, MIPI) and SPI configuration interface

Every core in this line is a product of LogikHaus's VHDL design process, architected, coded, and verified in VHDL by our FPGA and VHDL experts before being packaged as ASIC or FPGA IP.