VHDL for Synthesis — VHDL Design Training

Synopsis

What you will learn

• Familiarise with FPGA development tools for design entry, analysis and simulation (Gowin IDE, Xilinx Vivado, Altera Quartus, Mentor Graphics ModelSim, Synopsys VCS-MX)
• Know the fundamentals of VHDL design, with particular emphasis on synthesizable constructs (i.e. able to generate hardware)
• Describe combinational and sequential circuits in a structural and behavioural manner
• Develop digital systems in a hierarchical and modular nature to aid testing, debugging and hardware reuse
• Learn and use VHDL constructs for simulation and verification with testbenches
• Describe the operation of sequential circuits in the Register Transfer Level (RTL) notation
• Describe control flow with Finite-State Machines (FSM) and implement them in VHDL

Who should attend

Prerequisite

• Register Transfers and Sequencing in VHDL
• Transaction-level Modelling and Bus Functional Modelling
• Developing AMBA AXI-compliant Modules for System-On-Chip Designs

Course methodology

Course duration

Course structure

1. Introduction
   • IC/FPGA design flow
   • HDL design flow (front-end design)
   • History of VHDL
   • Key concepts, philosophy, and doctrine
   • Determinism
2. Basic VHDL 1
   • Basic language constructs
   • std_logic_1164 nine-value logic system
   • Operators
   • Data types and representation
   • VHDL's strong typing
   • Type safety: Benefits of strong typing
   • Type conversions
   • Hands-on Practical: My first VHDL design with Quartus II
3. Basic VHDL 2: VHDL Data Structures for Synthesis
   • Concept of scalar types vs. composite types
   • Custom data types: type, subtype
   • Synthesisable predefined data types and structures
   • New synthesisable data types from VHDL-2008
   • More on composite types: enumerated types, aggregates and array slices, record types
   • Concatenation
   • Repetition: functional and structural repetitions
   • RAMs and ROMs
   • Hands-on Practical: Design memory structures using VHDL arrays
4. Overview of Hardware Modelling Techniques
   • Behavioural vs. structural modelling
   • Behavioural modelling techniques: concurrent vs. sequential design
5. Structural Design for Synthesis
   • Structural HDL modelling
   • Component instantiation
   • Hands-on Practical: Instantiate a given component in your design
   • Direct-entity instantiation
   • Hands-on Practical: Directly instantiate a given submodule
   • Hands-on Practical: Directly embed a Gowin / Xilinx GTX / Altera GX transceiver IP core using VHDL
   • Hierarchical design and Modularisation
   • Basic generics (Parameterisation)
   • Automatic generation of repeating structures
   • Hands-on Practical: Iteratively duplicate a given submodule a specified number of times
6. Behavioural Design for Synthesis: Sequential Techniques
   • Register basics
   • Processes for synthesis
   • Sequential statements
   • Conditional signal assignments using sequential techniques
   • Verilog's blocking and non-blocking statements: a VHDL explanation
   • Process sensitivity lists
   • New matching conditional operators from VHDL-2008
   • Inference of the basic building blocks: registers, latches, multiplexers, and comparators
   • Hands-on Practical: Combinatorial logic using sequential techniques
   • Counters
   • Hands-on Practical: Design an up/down counter using sequential techniques
   • Shift registers
7. Behavioural Design for Synthesis: Concurrent Techniques
   • Concurrent statements
   • Conditional signal assignments using concurrent techniques
   • Hands-on Practical: Combinatorial logic using concurrent techniques
   • Hands-on Practical: Design an up/down counter using concurrent techniques


8. State Machines
   • Register transfer operations
   • Finite-state Machines (FSM)
   • Hands-on Practical: Design a serial transceiver (transmitter)
   • Hands-on Practical: Design a serial receiver
9. Basics of Functional Verification
   • Basic testbench methods
   • Hands-on Practical: Simulate with Synopsys VCS-MX
   • Hands-on Practical: Verify design on hardware with SignalTap
10. Overview of Advanced Topics
    • VHDL package design: create your own library
    • Subprograms: Functions & Procedures
    • Access types
    • Protected types and shared variables
    • Advanced generics: Type generics, Subprogram generics, Package generics
    • Configurations
    • Synthesis attributes (vendor-specific and predefined)
    • Synthesis pragmas/directives
    • IP source encryption
    • Custom resolution functions
    • Simulation-only techniques for testbench design: Files I/O, External/hierarchical names, Force and release assignments, Assertion-based verification (ABV), Constrained random verification (CRV), Functional coverage (FC)

Instructor

Advanced VHDL Design Applications

• Digital Signal Processing (DSP) design in VHDL
• Wireless Communications systems design in VHDL
• Register Transfers and Sequencing in VHDL
• Developing AMBA AXI-compliant Modules for System-On-Chip Designs

Frequently Asked Questions

Who teaches the VHDL design course at LogikHaus?

VHDL for Synthesis is taught by Daniel Kho, Founder and CTO of LogikHaus and a VHDL expert with over 24 years in FPGA design, ASIC design, and digital systems training across Southeast Asia.

Is this VHDL design course suitable for beginners?

Yes. This course is aimed at engineers new to the HDL flow who hold a diploma/degree in electronics or related engineering. It is the recommended prerequisite for our advanced VHDL design courses, including Register Transfers and Sequencing in VHDL and Developing AMBA AXI-compliant Modules.