VHDL Simulations and Testbenches
A 3-day, hands-on VHDL testbench and VHDL simulation course for engineers who need to verify FPGA and ASIC designs properly. Learn constrained random verification, assertions, scoreboards and the OSVVM framework using ModelSim/QuestaSim or Synopsys VCS-MX.
Synopsis
Commercial, professional and industrial digital systems keep growing in complexity as more features are integrated into them. With ever-shorter time-to-market and more systems used in safety-critical areas, engineers must make sure their complex designs are error-free and work as intended. This has made design verification, especially at the pre-silicon stage, a vital part of the design process.The need for a systematic approach to verifying digital systems has given rise to advanced testbench verification methodologies such as OSVVM, OVM, UVM and AVM. This VHDL design verification course, taught by our in-house VHDL expert, introduces the key testbench concepts and verification framework of OSVVM, which allow engineers to systematically and accurately validate designs with minimal test cases. The course covers the simulation of digital systems and the design of proper VHDL testbenches for verification. Ultimately, it equips engineers with a powerful toolset to make sure their designs are properly tested in a timely manner.
Course Highlights
Participants gain practical design experience using industry-standard logic simulators (e.g. Synopsys VCS-MX or Mentor Graphics QuestaSim/ModelSim), with six hands-on practical sessions.What You Will Learn in This VHDL Testbench Course
This course covers both theory and practice. Upon completing the course, participants will be able to:- Simulate digital circuits with Synopsys VCS-MX or Mentor Graphics ModelSim.
- Learn and use VHDL design constructs for simulation and verification.
- Design tester components such as stimuli / test vector generators, transaction monitors, response checkers, and scoreboards.
- Design testbench components using techniques such as simple assertions, file I/O, and constrained random verification (CRV).
- Have an overview of advanced techniques such as transaction-level modelling (TLM), bus functional modelling (BFM), temporal assertions-based verification (ABV), constrained random verification (CRV), and functional coverage.
Who Should Attend
This course is particularly suited for FPGA and ASIC engineers involved in HDL-flow digital design simulation, verification and testing.Prerequisites
Participants should have a diploma/degree in electronics (or related) engineering with an understanding of digital systems. Knowledge in VHDL/Verilog for developing synthesizable digital systems or simulation testbenches is helpful but not required.Course Methodology
This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practicals for maximum understanding.Course Duration
Three days, 0900 to 1700.Course Structure
- Introduction
- IC/FPGA design and verification flow.
- The Design Under Verification (DUV).
- Overview of testbench components.
- Stimuli vector generator design
- Concept of test vector generation, types of stimuli (directed, pseudorandom).
- Unconstrained vs. constrained randomisation.
- Unconstrained randomisation of stimuli.
- Hands-on Practical 1: Unconstrained random stimuli vector generator design and simulation.
- Constrained random verification (CRV).
- Hands-on Practical 2: Constrained random stimuli vector generator design and simulation.
- File I/O (input only).
- Hands-on Practical 3: Reading stimuli from a file.
- Transaction monitor design
- Concept of transaction monitoring.
- Simple (non-temporal) assertions-based verification (ABV).
- Hands-on Practical 4: Transaction monitor design using non-temporal assertions.
- Response checker design
- Concept of response checking.
- Scoreboards.
- Hands-on Practical 5: Response checker design using scoreboards logged to simulator's console.
- File I/O (output only).
- Hands-on Practical 6: Response checker design using scoreboards logged to a file.
- Overview of advanced testbench techniques
- Temporal assertions-based verification (ABV) with Property Specification Language (PSL).
- Functional coverage: an introduction to OSVVM's intelligent coverage-driven constrained randomisation.
- Transaction-level modelling (TLM) and bus functional modelling (BFM).
Instructor
This course is taught by Daniel Kho, Founder & CTO of LogikHaus and a VHDL expert who has built OSVVM and UVM verification frameworks for communications IP (FFT, QPSK/QAM, MIPI C-PHY) and cryptographic hardware in production designs.Advanced VHDL Design Applications
The verification techniques in this course apply directly to our expert-level, application-specific VHDL design courses:- Digital Signal Processing (DSP) design in VHDL
- Wireless Communications systems design in VHDL
- Register Transfers and Sequencing in VHDL
- Developing AMBA AXI-compliant Modules for System-On-Chip Designs
Frequently Asked Questions
- Who teaches VHDL simulation and verification at LogikHaus?
- VHDL Simulations and Testbenches is taught by Daniel Kho, Founder and CTO of LogikHaus and a VHDL expert who has built OSVVM and UVM verification frameworks for communications IP, video processing, and cryptographic hardware.
- Do I need prior VHDL design experience for this course?
- No. Knowledge of VHDL or Verilog is helpful but not required. Participants should have a diploma/degree in electronics or related engineering with an understanding of digital systems.
- How long is the VHDL testbench course?
- The course runs for three days, from 0900 to 1700 each day, and includes six hands-on practical sessions.
- Which simulators are used in the course?
- Participants work with industry-standard logic simulators such as Synopsys VCS-MX and Mentor Graphics QuestaSim/ModelSim.
- What is OSVVM and is it covered in this course?
- OSVVM (Open Source VHDL Verification Methodology) is a VHDL verification framework for constrained random stimuli, functional coverage and scoreboards. This course introduces its key concepts, including coverage-driven constrained randomisation.