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VHDL Subprograms for Synthesis and Simulations

A 2-day, hands-on VHDL subprograms course. Learn how to write and use VHDL functions and VHDL procedures that work in both simulation and synthesis, then go further with subprogram overloading, generics and impure functions using Vivado, Quartus and QuestaSim.

Synopsis

VHDL is a popular hardware description language, mostly used to describe and verify electronic circuits. This VHDL design course introduces the concept of subprograms, which are useful for both simulation and synthesis. Participants will understand what functions and procedures are, and be able to apply these concepts in real designs that involve digital simulation or synthesis.

Course Highlights

Participants gain practical design experience using industry-standard logic simulators (e.g. Synopsys VCS-MX or Mentor Graphics QuestaSim/ModelSim), logic synthesis tools (e.g. Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus), and development boards from either Altera or Xilinx.

What You Will Learn in This VHDL Subprograms Course

This course covers both theory and practice. Upon completing the course, participants will be able to:
  • Use subprograms for synthesis and simulation.
  • Use VHDL functions and procedures in digital designs.
  • Simulate and synthesise designs that use VHDL subprograms.

Who Should Attend

This course is particularly suited for FPGA and ASIC engineers involved in HDL-flow digital design, synthesis, simulation, verification and testing.

Prerequisites

Participants should have a diploma/degree in electronics (or related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesizable digital systems or simulation testbenches.

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practicals for maximum understanding.

Course Duration

Two days, 0900 to 1700.

Course Structure

  1. Introduction
    • Overview of subprograms.
    • When to use functions and procedures?
  2. VHDL Functions
    • Basic syntax of a function.
    • Hands-on Practical 1: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
    • Hands-on Practical 2: Synthesis with Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus.
  3. VHDL Procedures
    • Basic syntax of a procedure.
    • Hands-on Practical 3: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
    • Hands-on Practical 4: Synthesis with Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus.
  4. [optional]: Advanced Topics
    • Subprogram overloading.
    • Hands-on Practical 5: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
    • Hands-on Practical 6: Synthesis with Synopsys Design Compiler, Xilinx Vivado, or Altera Quartus.
    • Subprogram generics.
    • Hands-on Practical 7: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.
    • Impure functions.
    • Hands-on Practical 8: Simulation using Synopsys VCS-MX or Mentor Graphics QuestaSim.

Advanced VHDL Design Applications

The subprogram techniques in this course are a recommended prerequisite for our advanced VHDL design courses, including: Browse all courses on our Education page.

Frequently Asked Questions

What is the difference between a VHDL function and a procedure?
A VHDL function returns a single value and is used inside expressions. A procedure is called as a statement and can return multiple results through its out and inout parameters. This course covers when to use each, for both simulation and synthesis.
Do I need VHDL experience for this course?
Yes. Participants should be familiar with VHDL or Verilog for developing synthesizable digital systems or simulation testbenches, and hold a diploma/degree in electronics or related engineering.
Which tools are used in the hands-on practicals?
Simulation uses Synopsys VCS-MX or Mentor Graphics QuestaSim/ModelSim. Synthesis uses Synopsys Design Compiler, Xilinx Vivado or Altera Quartus, with Altera or Xilinx development boards.
How long is the VHDL subprograms course?
The course runs for two days, from 0900 to 1700 each day, with up to eight hands-on practical sessions.