Jeannie Lau is a parasitic extraction expert and ASIC LVS (layout-versus-schematic) expert with over 22 years of specialist experience built across roles at GLOBALFOUNDRIES, Intel and Primarius Technologies. She specialises in circuit analysis, RC extraction and static timing analysis (STA) across StarRC, xRC and Quantus/QRC flows.
As an ASIC EDA flow specialist, Jeannie has developed and qualified custom extraction and LVS flows against foundry PDKs down to 14nm and 10nm process nodes, including ITF/ICT/MIPT techfile development and multi-vendor extraction qualification. She was recognised with an Altera Innovator Award for her contribution to resolving capacitive shielding issues that affected signal integrity.
Her background spans debugging complex extraction problems (opens, shorts, large capacitance and PrimeTime back-annotation errors) and building Perl, Tcl and Python automation for ASIC and custom extraction flows. At LogikHaus, she leads analog design and verification at the PCB level, supporting our FPGA boards and custom PCB design, alongside hardware debug and embedded system verification. Her ASIC design enablement experience also strengthens LogikHaus's ASIC and FPGA design services.
Project Highlights
Resolving Capacitive Shielding Issues in Skipcells-Based Layouts
A capacitive shielding issue caused by the skipcells methodology was distorting extracted capacitance values, risking signal integrity failures that would not surface until later in the design cycle. Jeannie contributed to a robust solution, correcting the extraction methodology to accurately capture the coupling effects introduced by the layout. The work was recognised with an Altera Innovator Award.
Multi-Vendor Extraction Flow Qualification Down to 10nm
Extraction results can vary meaningfully between vendor tools (StarRC, xRC, Quantus/QRC) depending on how each interprets a foundry's interconnect technology files. Jeannie built and qualified extraction and LVS flows across these tools against foundry PDKs down to 14nm and 10nm, developing ITF/ICT/MIPT techfiles and Perl/Tcl automation to catch opens, shorts and large-capacitance discrepancies before they reached tape-out.
Areas of Expertise
Frequently Asked Questions
Who is Jeannie Lau?
Jeannie Lau is Principal Analogue Microelectronics Engineer at LogikHaus, a parasitic extraction and ASIC LVS specialist with over 22 years of experience at GLOBALFOUNDRIES, Intel and Primarius Technologies.
What does Jeannie Lau specialise in?
Parasitic extraction, circuit analysis, static timing analysis and ASIC LVS (layout-versus-schematic) verification. She has developed and qualified extraction and LVS flows against foundry PDKs down to 14nm and 10nm process nodes.
Which parasitic extraction tools does Jeannie Lau work with?
She has built and qualified extraction flows across StarRC, xRC and Quantus/QRC, including ITF/ICT/MIPT techfile development and PrimeTime back-annotation, with Perl, Tcl and Python automation.
What does Jeannie Lau do at LogikHaus?
At LogikHaus she leads analog design and verification at the PCB level, along with hardware debug and embedded system verification, and brings her ASIC design enablement background to the company's ASIC design work.