Jeannie Lau is a parasitic extraction expert and ASIC LVS expert (layout-versus-schematic verification), with over 22 years of specialist experience built across roles at GLOBALFOUNDRIES, Intel, and Primarius Technologies. She specializes in circuit analysis, RC extraction, and static timing analysis (STA) across StarRC, xRC, and Quantus/QRC flows.
As an ASIC EDA flow specialist, Jeannie has developed and qualified custom extraction and LVS flows against foundry PDKs down to 14nm and 10nm process nodes, working across ITF/ICT/MIPT techfile development and multi-vendor extraction qualification (StarRC, xRC, Quantus). She holds an Altera Innovator Award for her work resolving capacitive shielding issues affecting signal integrity.
Her background spans debugging complex extraction problems — opens, shorts, large capacitance, and PrimeTime back-annotation errors — and building Perl, Tcl, and Python-based automation for ASIC and custom extraction flows. At LogikHaus, she leads analog design and verification at the PCB level, alongside hardware debug and embedded system verification.
Project Highlights
Resolving Capacitive Shielding Issues in Skipcells-Based Layouts
A capacitive shielding issue caused by the skipcells methodology was distorting extracted capacitance values, risking signal integrity failures that wouldn't surface until later in the design cycle. Jeannie contributed to developing a robust solution to the shielding problem, correcting the extraction methodology to accurately capture coupling effects introduced by the layout. The work was recognised with an Altera Innovator Award.
Multi-Vendor Extraction Flow Qualification Down to 10nm
Extraction results can vary meaningfully between vendor tools (StarRC, xRC, Quantus/QRC) depending on how each interprets a foundry's interconnect technology files. Jeannie built and qualified extraction and LVS flows across these vendors against foundry PDKs down to 14nm and 10nm process nodes — developing ITF/ICT/MIPT techfiles and Perl/Tcl-based automation to catch opens, shorts, and large-capacitance discrepancies before they reached tape-out.
Areas of Expertise
Frequently Asked Questions
- Who is Jeannie Lau?
- Jeannie Lau is Principal Analogue Microelectronics Engineer at LogikHaus, a parasitic extraction and ASIC LVS specialist with over 22 years of experience at GLOBALFOUNDRIES, Intel, and Primarius Technologies.
- What does Jeannie Lau specialize in?
- Jeannie specializes in parasitic extraction, circuit analysis, static timing analysis, and ASIC LVS (layout-versus-schematic) verification, and has developed and qualified extraction and LVS flows against foundry PDKs down to 14nm and 10nm process nodes.